The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique including a method and a structure for forming multi-layered substrate structures using bonding techniques for the fabrication of semiconductor integrated circuit devices. Such bonding techniques include use of thermal processing to establish bonded interfaces that are substantially free of imperfections, defects, and/or other undesirable features according to a specific embodiment. In a preferred embodiment, the thermal processing causes oxygen species to be transferred from an interface region between a bonded pair to be removed to an outer region. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other types of substrates for three-dimensional packaging of integrated semiconductor devices, photonic devices, piezoelectronic devices, flat panel displays, microelectromechanical systems (“MEMS”), nano-technology structures, sensors, actuators, solar cells, biological and biomedical devices, and the like.
From the very early days, human beings have been building useful articles, tools, or devices using less useful materials for numerous years. In some cases, articles are assembled by way of smaller elements or building blocks. Alternatively, less useful articles are separated into smaller pieces to improve their utility. A common example of these articles to be separated include substrate structures, such as a glass plate, a diamond, a semiconductor substrate, a flat panel display, and others. These substrate structures are often cleaved or separated using a variety of techniques. In some cases, the substrates can be separated using a saw operation. The saw operation generally relies upon a rotating blade or tool, which cuts through the substrate material to separate the substrate material into two pieces. This technique, however, is often extremely “rough” and cannot generally be used for providing precision separations in the substrate for the manufacture of fine tools and assemblies. Additionally, the saw operation often has difficulty separating or cutting extremely hard and or brittle materials, such as diamond or glass. The saw operation also cannot be used effectively for the manufacture of microelectronic devices, including integrated circuit devices, and the like.
Accordingly, techniques have been developed to fabricate microelectronic devices, commonly called semiconductor integrated circuits. Such integrated circuits are often developed using a technique called the “planar process” developed in the early days of semiconductor manufacturing. An example of one of the early semiconductor techniques is described in U.S. Pat. No. 2,981,877, in the name of Robert Noyce, who has been recognized as one of the fathers of the integrated circuit. Such integrated circuits have evolved from a handful of electronic elements into millions and even billions of components fabricated on a small slice of silicon material. Such integrated circuits have been incorporated into and control many of today's devices, such as computers, cellular phones, toys, automobiles, and all types of medical equipment.
Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits. Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer.
Making devices smaller is very challenging, as each process used in integrated circuit fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials. An example of such a process is an ability to make the thickness of the substrate thin after the manufacture of the integrated circuit devices thereon. A conventional process often used to thin these device layers is often called “back grinding,” which is often cumbersome, prone to cause device failures, and can only thin the device layer to a certain thickness. Although there have been significant improvements, such back grinding processes still have many limitations.
Accordingly, certain techniques have been developed to cleave a thin film of crystalline material from a larger donor substrate portion. These techniques are commonly known as “layer transfer” processes. Such layer transfer processes have been useful in the manufacture of specialized substrate structures, such as silicon on insulator or display substrates. As merely an example, a pioneering technique was developed by Francois J. Henley and Nathan Chung to cleave films of materials. Such technique has been described in U.S. Pat. No. 6,013,563 titled Controlled Cleaving Process, assigned to Silicon Genesis Corporation of San Jose, Calif., and hereby incorporated by reference for all purposes. Although such technique has been successful, there is still a desire for improved ways of manufacturing multilayered structures.
From the above, it is seen that a technique for manufacturing large substrates which is cost effective and efficient is desirable.